1. Field
Exemplary embodiments of the present invention relate to a signal shifting circuit, a base chip, and a semiconductor system including the same.
2. Description of the Related Art
FIG. 1 is a diagram showing a semiconductor system including a plurality of chips including a base chip BASE and four core chips CORE0 to CORE3.
The core chips CORE0 to CORE3 are sequentially stacked over a base chip BASE. Each core chip includes a plurality of memory banks (not shown). The base chip BASE is responsible for external communication with a semiconductor package. The base chip BASE may generate signals for controlling the plurality of core chips CORE0 to CORE3 in response to externally provided commands and addresses and may send the generated signals to the respective core chips CORE0 to CORE3 through the through vias TSVs or transfer data between the plurality of core chips CORE0 to CORE3 and external devices.
The semiconductor system typically uses a data strobe signal in order to accurately recognize externally provided data during a write operation. The data strobe signal is transmitted from a chipset to the semiconductor package along with data, and toggles between two states during one clock cycle. Data and an external clock are transmitted from the chipset to the semiconductor memory device through different transmission lines. An error is generated in the recognition of the data due to a difference in the transmission speed of the different transmission lines. Accordingly, the chipset transfers the data strobe signal to the semiconductor system through a transmission line for the data strobe signal, which is similar to a transmission line for the transmission of the data. Strobe signal encoding allows the semiconductor system to more accurately recognize the data.
In the case of the semiconductor system including the plurality of chips as shown in FIG. 1, data and a data strobe signal are provided to the core chips CORE0 to CORE3 through the base chip BASE. Therefore, each of the core chips CORE0 to CORE3 needs to receive a portion of the data strobe signal because the data strobe signal is transferred from the base chip BASE to all of the core chips CORE0 to CORE3. In this case, a margin may be reduced due to a phase difference between the internal clock of the semiconductor system and the data strobe signal.